ST

n.n. Model Package
1 EF6802P PDIP-40
2 MK38P70 (MK97501R-00) 40-pin side-brazed piggyback CDIP
3 MK38P70/02D1 (MK97501R-00) 40-pin side-brazed piggyback CDIP

1

 EF6802P 

2

 MK38P70

           3

 MK38P70/02D1 (MK97501R-00) 

  Frequency:
Data bus width:
On-chip RAM:
On-chip ROM:
Memory Addressing:
Vcc:
Temperature range:
1 MHz
8 bit
128 bit
No
16 bit
5 V
(0-70)°C
            Frequency:
Data bus width:
Physical memory range:
On-chip peripherals:

Vcc:
4 MHz
8 bit
64 KB
Programmable binary timer
(5 ± 10%) V

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